Improved PBTI Reliability in Junction-Less FET Fabricated at Low Thermal Budget for 3-D Sequential Integration

Junction-less FETs are used as top-tier devices in a 3-D sequential integration. Due to the low thermal budget allowed in the 3-D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, a junctionless FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We observe that the reliability of junction-less FETs can be further improved by increasing the channel doping and/or the channel thickness. Correspondingly, a tradeoff exists between performance (subthreshold slope, carrier mobility), reliability, and variability. This tradeoff is verified in both planar/FinFET structures and can serve as a device optimization matrix. Furthermore, we use the non-radiative multi-phonon (NMP) theory, as implemented in the imec/T.U. Vienna BTI simulation framework "Comphy," to investigate the degradation kinetics and show that the stress/recovery traces measured in inversion mode and junction-less nFETs can be reproduced with the same set of oxide defect parameters. This observation confirms that the reliability improvement in junction-less devices is inherent to their specific operation mode and not related to the different fabrication flows compared to standard inversion mode devices. Based on the calibrated Comphy model, we perform BTI lifetime projections, exposing for junction-less devices a substantial deviation from the commonly used power-law voltage acceleration.