STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks

被引:38
|
作者
Afifi, Ahmad [1 ]
Ayatollahi, Ahmad [1 ]
Raissi, Farshid [2 ]
机构
[1] Iran Univ Sci & Technol, EE Dept, Tehran, Iran
[2] KN Toosi Univ Technol, ECE Dept, Tehran, Iran
来源
IEICE ELECTRONICS EXPRESS | 2009年 / 6卷 / 03期
关键词
CMOL; memristive; neuromorphic networks; STDP learning;
D O I
10.1587/elex.6.148
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Implementation of a correlation-based learning rule, Spike-Timing- Dependent-Plasticity (STDP), for asynchronous neuromorphic networks is demonstrated using 'memristive' nanodevice. STDP is performed using locally available information at the specific moment of time, for which mapping to crossbar-based CMOS-Nano architectures, such as CMOS-MOLecular (CMOL), is done rather easily. The learning method is dynamic and online in which the synaptic weights are modified based on neural activity. The performance of the proposed method is analyzed for specifically shaped spikes and simulation results are provided for a synapse with STDP properties.
引用
收藏
页码:148 / 153
页数:6
相关论文
共 12 条
  • [1] Efficient Hybrid CMOS-Nano Circuit Design for Spiking Neurons and Memristive Synapses with STDP
    Afifi, Ahmad
    Ayatollahi, Ahmad
    Raissi, Farshid
    Hajghassem, Hasan
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2010, E93A (09) : 1670 - 1677
  • [2] Implementation of STDP based learning rule in Neuromorphic CMOS Circuits
    Srinidhi, P. J.
    Yashaswini, T. R.
    Uttunga, N.
    Ali, Syed Aslam
    Ahmed, Mohammed Riyaz
    2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICICCS), 2017, : 1105 - 1110
  • [3] rFPGA: CMOS-nano hybrid FPGA using RRAM components
    Liu, Ming
    Wang, Wei
    2008 IEEE INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES, 2008, : 93 - +
  • [4] Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons
    Vohra, Sahibia Kaur
    Thomas, Sherin A.
    Sakare, Mahendra
    Das, Devarshi Mrinal
    INTEGRATION-THE VLSI JOURNAL, 2024, 95
  • [5] Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
    Mohan, C.
    Camunas-Mesa, L. A.
    de la Rosa, J. M.
    Serrano-Gotarredona, T.
    Linares-Barranco, B.
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [6] Implementation of STDP for Spintronics based SNN using 90nm CMOS Technology
    Kuruvithadam, Rose Mary
    Nalesh, S.
    2022 IEEE 19TH INDIA COUNCIL INTERNATIONAL CONFERENCE, INDICON, 2022,
  • [7] Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses
    Thomas, Sherin A.
    Vohra, Sahibia Kaur
    Kumar, Rahul
    Sharma, Rohit
    Das, Devarshi Mrinal
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2022, 21 : 380 - 389
  • [8] Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit
    Kwon, Min-Woo
    Baek, Myung-Hyun
    Hwang, Sungmin
    Kim, Sungjun
    Park, Byung-Gook
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2018, 18 (09) : 6588 - 6592
  • [9] STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing
    Srinivasan, Gopalakrishnan
    Panda, Priyadarshini
    Roy, Kaushik
    ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2018, 14 (04)
  • [10] Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology
    Kumaresan, Raja Sekar
    Raj, Marshal
    Gopalakrishnan, Lakshminarayanan
    JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS, 2022, 73 (01): : 1 - 10