Electrical Characteristics of 14nm SiC-3C Channel SOI FinFET with Dual-k Spacer

FinFETs have been the most promising replacement of MOSFETs for nanoscale era. Below 20nm, performance is highly degraded due to severe short channel effects (SCEs). In this paper, the electrical performance of SOI FinFET has been examined at 14nm gate length. Channel material used is SiC-3C because of its high carrier transport. Dual-k spacers are used in the underlap region between gate and source/drain. Density gradient quantum correction model has been used in simulations to include quantum mechanical (QM) effects in the nanoscale device. Also, dependence of high field effects on mobility has been taken into account. Input parameters like buried oxide thickness, m pound height and fin thickness were varied to analyze their impact on output parameters i.e. on current (I-on), off current (I-off), on/off ratio (I-on/I-off) and Subthreshold Swing (SS). It was observed that highest I-on of 1.128e-05 is achieved for H-fin =24nm and T-fin =8nm, leakage current obtained is 5.629e-15 for H-fin =16nm and T-fin = 4nm, on/off current is of the order of 1e08. Minimum SS is 62mV/dec for thin fins of designed SOI FinFET.