Electroplating Cu fillings for through-vias for three-dimensional chip stacking

被引：5

作者：

Tomisaka, M ^{[1
]}

Yonemura, H ^{[1
]}

Hoshino, M ^{[1
]}

Takahashi, K ^{[1
]}

Okamura, T ^{[1
]}

Sun, RJ ^{[1
]}

Kondo, K ^{[1
]}

机构：

[1] Assoc Super Adv Elect Technol ASET, Elect Syst Integrat Technol Res Dept, Tsukuba, Ibaraki 3050047, Japan

来源：

52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/ECTC.2002.1008294

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Three-dimensional (3D) LSI chip stacking with through chip electrodes can realize high-density packaging and highspeed operation performance because the through chip electrode offers the shortest interconnection between stacked chips. The through chip via size we studied was 10-mum-square and 70-mum-deep. The void free plating is necessary to avoid troubles caused by acid solutions remained in voids. In this paper, systematic studies of the dependence of electroplating conditions on via filling are described. We found that vias could be almost filled up.

引用

页码：1432 / +

页数：3

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