Algorithm and VLSI Architecture of Channel Estimation Impaired by Impulsive Noise in PLC

被引:0
|
作者
Chen, Yun [1 ]
Zhang, Qiang [1 ]
Ge, Yunlong [1 ]
Hu, Yuanzhou [1 ]
Chen, Jie [1 ]
Ding, Na [1 ]
Zeng, Xiaoyang [1 ]
Huang, Defeng [2 ]
机构
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
[2] Univ Western Australia, Crawley, WA, Australia
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we investigate the channel estimation algorithm for medium-voltage, long haul power line communi-cation (PLC) system in the IEEE 1901 standard. To improve the overall performance, we employ a dual Gaussian interpolation method working on the amplitude and phase domain simultane-ously, a major difference from the conventional schemes using the real and imaginary part. Meanwhile, to mitigate the effect of impulsive noise, a notorious impairment in PLC transmission, we propose an impulsiveness detection/cancellation method using unused null subcarriers. Extensive simulation results indicate improved performance than the conventional inter-polators in an impulsive environment. The channel models proposed by the open power-line communication European research alliance (OPERA) are utilized for simulation. The hardware architecture is also presented together with its achievable performance.
引用
收藏
页码:932 / 935
页数:4
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