Cache-Aware Approximate Computing for Decision Tree Learning

被引:3
|
作者
Kislal, Orhan [1 ]
Kandemir, Mahmut T. [1 ]
Kotra, Jagadish [1 ]
机构
[1] Penn State Univ, University Pk, PA 16802 USA
关键词
LOCALITY;
D O I
10.1109/IPDPSW.2016.116
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The memory performance of data mining applications became crucial due to increasing dataset sizes and multi-level cache hierarchies. Decision tree learning is one of the most important algorithms in this field, and numerous researchers worked on improving the accuracy of model tree as well as enhancing the overall performance of the learning process. Most modern applications that employ decision tree learning favor creating multiple models for higher accuracy by sacrificing performance. In this work, we exploit the flexibility inherent in decision tree learning based applications regarding performance and accuracy tradeoffs, and propose a framework to improve performance with negligible accuracy losses. This framework employs a data access skipping module (DASM) using which costly cache accesses are skipped according to the aggressiveness of the strategy specified by the user and a heuristic to predict skipped data accesses to keep accuracy losses at minimum. Our experimental evaluation shows that the proposed framework offers significant performance improvements (up to 25%) with relatively much smaller losses in accuracy (up to 8%) over the original case. We demonstrate that our framework is scalable under various accuracy requirements via exploring accuracy changes over time and replacement policies. In addition, we explore NoC/SNUCA systems for similar opportunities of memory performance improvement.
引用
收藏
页码:1413 / 1422
页数:10
相关论文
共 50 条
  • [31] CANR: CACHE-AWARE NAME-BASED ROUTING
    Hu, Xiaoyan
    Gong, Jian
    2014 IEEE 3rd International Conference on Cloud Computing and Intelligence Systems (CCIS), 2014, : 212 - 217
  • [32] A Cache-Aware Data Structure for Representing Boolean Polynomials
    Castro Campos, R. A.
    Sagols Troncoso, F. D.
    Zaragoza Martinez, F. J.
    2015 12TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTING SCIENCE AND AUTOMATIC CONTROL (CCE 2015), 2015,
  • [33] Cache-Aware Routing in Information-Centric Networks
    Sourlas, Vasilis
    Flegkas, Paris
    Tassiulas, Leandros
    2013 IFIP/IEEE INTERNATIONAL SYMPOSIUM ON INTEGRATED NETWORK MANAGEMENT (IM 2013), 2013, : 582 - 588
  • [34] Cache-aware real-time disk scheduling
    Chang, Hsung-Pin
    Chang, Ray-I
    Shih, Wei-Kuan
    Chang, Ruei-Chuan
    Computer Journal, 2004, 47 (05): : 560 - 578
  • [35] Cache-aware real-time disk scheduling
    Chang, HP
    Chang, RI
    Shih, WK
    Chang, RC
    COMPUTER JOURNAL, 2004, 47 (05): : 560 - 578
  • [36] Cache-aware scheduling of scientific workflows in a multisite cloud
    Heidsieck, Gaetan
    de Oliveira, Daniel
    Pacitti, Esther
    Pradal, Christophe
    Tardieu, Francois
    Valduriez, Patrick
    FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2021, 122 : 172 - 186
  • [37] WCET-driven Cache-aware Code Positioning
    Falk, Heiko
    Kotthaus, Helena
    PROCEEDINGS OF THE PROCEEDINGS OF THE 14TH INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURES AND SYNTHESIS FOR EMBEDDED SYSTEMS (CASES '11), 2011, : 145 - 154
  • [38] Cache-aware Schedulability Analysis of PREM Compliant Tasks
    Rashid, Syed Aftab
    Awan, Muhammad Ali
    Souto, Pedro F.
    Bletsas, Konstantinos
    Tovar, Eduardo
    PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, : 1269 - 1274
  • [39] Cache-aware network-on-chip for chip multiprocessors
    Tatas, Konstantinos
    Kyriacou, Costas
    Dekoulis, George
    Demetriou, Demetris
    Avraam, Costas
    Christou, Anastasia
    VLSI CIRCUITS AND SYSTEMS IV, 2009, 7363
  • [40] A Cache-Aware Performance Prediction Framework for GPGPU Computations
    Poeppl, Alexander
    Herz, Alexander
    EURO-PAR 2015: PARALLEL PROCESSING WORKSHOPS, 2015, 9523 : 749 - 760