Reversed double pole-zero cancellation frequency compensation technique for three-stage amplifiers

A novel frequency compensation technique for three-stage amplifiers is introduced. The proposed solution exploits two Miller capacitors, two resistors and an additional feedforward stage which can be implemented without entailing extra transistors. Design equations using the phase margin as design parameter are carried out. The technique is used to design, with a standard CMOS 035-mu m process, a 2-V three-stage amplifier driving a 500-pF load capacitor. The amplifier dissipates only 70 mu A at DC and achieves a 1.2-MHz gain-bandwidth product, showing a significant improvement in (MHz(.)pF)/mA performance.