Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction

被引:3
|
作者
Agarwal, Sukarn [1 ]
Kapoor, Hemangee K. [1 ]
机构
[1] IIT Guwahati, Dept CSE, Gauhati 781039, Assam, India
关键词
Non-volatile Memories; Lifetime; Write variation; STT-RAM; INTER;
D O I
10.1145/3299874.3317987
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The emerging Non-Volatile Memory (NVM) technologies offer a good combination of high density and near-zero leakage power, becoming the strongest candidate in the memory hierarchy including caches. However, the weak write endurance of these memories creates a bottleneck towards their employment in the cache hierarchy. This weak endurance shows its effects due to the write variations introduced by the applications and the existing cache management policies. Such variations result in early breakdown of the NVM cells reducing the effective lifetime of the NVM memory component. This paper proposes a technique to mitigate intra-set write variation, i.e. write variations occurring within the cache set. Our policy divides the cache logically into multiple equal-sized modules. During execution, the writes are distributed uniformly across different ways of the different modules within the set. Experimental results using full system simulation show that the proposed technique reduces the intra-set write variation significantly over the baseline and the existing techniques.
引用
收藏
页码:213 / 218
页数:6
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