Process window OPC verification: Dry versus immersion lithography for the 65 nm node.

被引:0
|
作者
Borjon, Amandine [1 ,2 ,3 ,4 ,5 ]
Belledent, Jerome [1 ]
Trouiller, Yorick [3 ]
Lucas, Kevin [2 ]
Couderc, Christophe [1 ]
Sundermann, Frank [4 ]
Urbani, Jean-Christophe [4 ]
Rody, Yves [1 ]
Gardin, Christian [2 ]
Foussadier, Frank [4 ]
Schiavone, Patrick [5 ]
机构
[1] Philips Semicond, 850 Rue J Monnet, F-38926 Crolles, France
[2] Freescale Semicond, F-38926 Crolles, France
[3] CEA, LETI, F-38054 Grenoble, France
[4] STMicroelectronics, F-38926 Crolles, France
[5] CEA Grenoble, CNRS, LTM, F-38054 Grenoble 09, France
来源
关键词
OPC; resist modelling; process window; ORC; failure prediction;
D O I
10.1117/12.657056
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 rim node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.
引用
收藏
页码:U2473 / U2483
页数:11
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