Interconnection networks for sea-of-gates VLSI: Comparative analysis of performance and complexity

This paper analyzes the problem of mapping the topology of interconnection networks for parallel processing, onto one new type of VLSI structures, known as the advanced sea-of-gates VLSI. The current research, in the domain of mapping the topology of interconnection networks, implies classical implementations on the basis of standard VLSI structures, connected in three-dimensional space: formulae for the performance and complexity are known for all eight types of interconnection networks, which according to Siegel's classification, represent the whole set of interconnection network classes. In this paper, we have used the ''heuristic'' mapping methodology, known as the Y methodology. We have found the formulae for the performance and the complexity for the sea-of-gates VLSI structures, where all connections are realized on the chip, in a two-dimensional space. It is shown that, when the technology changes, the formulae for the performance and the complexity also change, i.e. the ranking of interconnection networks far a given algorithm is different, when the technology changes from the classical VLSI technology, to the sea-of-gates VLSI technology.