FPGA implementations of the ICEBERG block cipher

被引：12
|
作者：
Standaert, F. -X. [1 ]
Piret, G. [1 ]
Rouvroy, G. [1 ]
Quisquater, J. -J. [1 ]
机构：
[1] Catholic Univ Louvain, Crypto Grp, B-1348 Louvain, Belgium
来源：
INTEGRATION-THE VLSI JOURNAL | 2007年 / 40卷 / 01期
关键词：
block ciphers; hardware implementations; FPGAs; ENCRYPTION; DES;
D O I：
10.1016/j.vlsi.2005.12.008
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents field programmable gate array (FPGA) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt (E/D) mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and E/D agility allow considering new encryption modes to counteract certain side-channel attacks. (C) 2006 Elsevier B.V. All rights reserved.
引用
收藏
页码：20 / 27
页数：8
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