Two-dimensional breakdown voltage analysis and optimal design of a silicon microstrip detector passivated by a dielectric

In this paper, we present a two-dimensional computer-based analysis. We study extensively the influence of various parameters, such as the permittivity of the passivant dielectric, the passivation layer thickness, the junction depth, the n-layer thickness and the fixed oxide charge, on the breakdown voltage of the dielectric passivated silicon microstrip detector. The relative permittivity of the passivant dielectric layer deposited over the oxide influences the breakdown voltage once some minimum value of passivation layer thickness has been reached. The breakdown voltage of shallow junction devices remains nearly constant over a wide variation in passivation layer thickness. It is shown that, for deeper junction devices, the breakdown voltage remains almost constant up to a particular passivant layer thickness and then increases sharply. The effects of device depth and fixed oxide charge on the passivated device are also analysed. Based on this T-CAD simulation, we propose a layout for a detector protection structure with optimized performance. The design presently envisaged offers decisive advantages over a number of possible alternatives in silicon detector technology. We have found good agreement between previous experimental data and the simulation results.