A 6-bit 0.81mW 700-MS/s SAR ADC with Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration

This paper presents a 6-b high-speed SAR ADC with sparkle code correction. By quantizing the comparator decision time (CDT), the sparkle codes are identified and corrected, reducing the error rate from 10(-4) to below 10(-9). Furthermore, CDT quantization enables 1-bit increase in the ADC resolution by setting the detection boundary to be +/- 0.25 LSB. Thus, only 5 comparison cycles are needed to reach 6-b, leading to increased ADC speed. The DAC also only needs to be 5-b, resulting in reduced chip area and faster settling. A novel dither-based background calibration technique is devised to accurately control the CDT detection window size and ensure PVT robustness. A prototype ADC in 40nm CMOS achieves 35.3dB SNDR and consumes 0.81mW while sampling at 700MS/s.