The verification and simulation of hardware description language

被引：0
|
作者：
Wang, Y [1 ]
Zhang, WJ [1 ]
Lu, P [1 ]
机构：
[1] Mech Engn Coll, Shijiazhuang 050003, Peoples R China
来源：
ICEMI'2001: FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT AND INSTRUMENTS, VOL 1, CONFERENCE PROCEEDINGS | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The verification and simulation method and process of designing with Hardware Description Language are introduced. Combining with VHDL, the testbenche and its simulation theory are discussed. This paper also discusses the method and steps of structuring a HDL testbenche in detail.
引用
收藏
页码：356 / 360
页数：5
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