Simple digital algorithm for improved performance in a boost PFC converter operating in CCM

In power factor correction (PFC) converters, achieving both good steady-state input current waveform and fast output dynamic response is a challenge. This is due to the effect of the double-line frequency ripple present in the sensed output voltage signal which tends to distort the reference current applied to the current controller, thus leading to a distorted input current waveform. Low bandwidth (BW) voltage loop designs to reduce this input current distortion make the output dynamic response very sluggish. A digital control algorithm for the estimation of the average value of the sensed output voltage is proposed in this study to achieve low total harmonic distortion input current and fast dynamic response with a higher BW voltage loop. The proposed algorithm is computationally less intensive and requires no additional sensors or circuitry. The effectiveness of the proposed control algorithm is validated through simulation and experimental tests on a 300 W boost PFC converter prototype operating in continuous conduction mode.