Development of a Highly Efficient and Linear Differential CMOS Power Amplifier With Harmonic Control

被引：0

作者：

Jin, Sangsu ^{[1
]}

Moon, Kyunghoon ^{[1
]}

Kwon, Myeongju ^{[3
]}

Park, Byungjoon ^{[2
]}

Jin, Hadong ^{[1
]}

Park, Jongjin ^{[2
]}

Kim, Bumman ^{[1
,2
]}

机构：

[1] POSTECH, Dept Elect Engn, Pohang 790784, Gyeongbuk, South Korea

[2] POSTECH, Div IT Convergence Engn, Pohang 790784, Gyeongbuk, South Korea

[3] LG Elect, CTO, Syst IC Lab, Seoul 137130, South Korea

来源：

2013 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC 2013) | 2013年

基金：

新加坡国家研究基金会;

关键词：

Cascode; differential; long term evolution (LTE); linearization; power amplifiers (PAs); second harmonic control;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with a second harmonic circuit at the common-gate (CG) stage. The proposed single stage PA including the harmonic control circuit is fabricated using 0.18-mu m RF CMOS technology with a printed board circuit based output transformer. The impact on the nonlinearity of the common-gate stage is analyzed. The CMOS PA module achieves a power added efficiency (PAE) of 38.7%, an error vector magnitude (EVM) of 5.4%, and the adjacent channel leakage ratio (ACLR) of -30.4 dBc at the average output power of 27.8 dBm and the frequency of 1.85 GHz for the 10-MHz bandwidth (BW) 16-QAM 7.5-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal.

引用

页码：757 / 759

页数：3

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