1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks

被引:105
|
作者
Magnone, P. [1 ]
Crupi, F. [1 ]
Giusi, G. [1 ]
Pace, C. [1 ]
Simoen, E. [2 ]
Claeys, C. [2 ,3 ]
Pantisano, L. [2 ]
Maji, D. [4 ]
Rao, V. Ramgopal [4 ]
Srinivasan, P. [5 ]
机构
[1] Univ Calabria, Dipartimento Elettron Informat & Sistemist, I-87036 Cosenza, Italy
[2] Interuniv Microelect Ctr, B-3001 Louvain, Belgium
[3] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Louvain, Belgium
[4] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
[5] Texas Instruments Inc, Dallas, TX 75243 USA
关键词
Drain noise; gate noise; high-k dielectric; MOSFET; 1/f noise; LOW-FREQUENCY NOISE; FLICKER NOISE; IMPACT; BEHAVIOR; DIELECTRICS; NMOSFETS; MOBILITY; DEFECTS; PERFORMANCE; TRANSISTORS;
D O I
10.1109/TDMR.2009.2020406
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
引用
收藏
页码:180 / 189
页数:10
相关论文
共 50 条
  • [21] Carrier scattering in high-k/metal gate stacks
    Zeng, Zaiping
    Triozon, Francois
    Niquet, Yann-Michel
    JOURNAL OF APPLIED PHYSICS, 2017, 121 (11)
  • [22] Extraction of Trap Parameters for High-K Gate Stacks
    Kar, S.
    Rawat, S.
    PHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 6, 2008, 16 (05): : 111 - 120
  • [23] Band engineering in the high-k dielectrics gate stacks
    Wang, S. J.
    Dong, Y. F.
    Feng, Y. P.
    Huan, A. C. H.
    MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2332 - 2335
  • [24] Theoretical analysis of high-k dielectric gate stacks
    Demkov, A. A.
    Sharia, O.
    Lee, J. K.
    MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2032 - 2034
  • [25] On the 1/f noise of triple-gate field-effect transistors with high-k gate dielectric
    Lukyanchikova, N.
    Garbar, N.
    Kudina, V.
    Smolanka, A.
    Put, S.
    Claeys, C.
    Simoen, E.
    APPLIED PHYSICS LETTERS, 2009, 95 (03)
  • [26] Simulation and Drain Current Performance analysis of High-K Gate Dielectric FinFET
    M. Aditya
    K. Srinivasa Rao
    K. Girija Sravani
    Koushik Guha
    Silicon, 2022, 14 : 4075 - 4078
  • [27] Simulation and Drain Current Performance analysis of High-K Gate Dielectric FinFET
    Aditya, M.
    Rao, K. Srinivasa
    Sravani, K. Girija
    Guha, Koushik
    SILICON, 2022, 14 (08) : 4075 - 4078
  • [28] Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs
    Jang, Junyong
    Lim, Towoo
    Kim, Youngmin
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2009, 24 (10)
  • [29] Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier/gate-induced drain leakage alternating stress
    Kim, Dongwoo
    Lee, Seonhaeng
    Kim, Cheolgyu
    Lee, Chiho
    Park, Jeongsoo
    Kang, Bongkoo
    MICROELECTRONICS RELIABILITY, 2012, 52 (9-10) : 1901 - 1904
  • [30] Extraction of Drain Current Thermal Noise in a 28 nm High-k/Metal Gate RF CMOS Technology
    Zhang, Huaiyuan
    Niu, Guofu
    Liang, Qingqing
    Imura, Kimihiko
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (06) : 2393 - 2399