共 50 条
- [1] A robust 0.15 mu m CMOS technology with CoSi2 salicide and shallow trench isolation [J]. 1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 125 - 126
- [2] New CoSi2 silicidation process demonstrated for 0.13 μm [J]. INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 1998, 28 (04): : 251 - 251
- [3] Full silicidation process for making CoSi2 on SiO2 [J]. APPLIED PHYSICS LETTERS, 2004, 84 (17) : 3292 - 3294
- [4] Electrical Analysis of Mechanical Stress Induced by Shallow Trench Isolation [J]. 2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 1155 - 1158
- [5] Electrical analysis of mechanical stress induced by shallow trench isolation [J]. ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 359 - 362
- [7] The study of diffusion and nucleation for COSi2 formation by oxide-mediated cobalt silicidation [J]. SURFACE & COATINGS TECHNOLOGY, 2006, 200 (10): : 3314 - 3318
- [8] Effect of shallow trench isolation induced stress on CMOS transistor mismatch [J]. 2004 IEEE International Conference on Semiconductor Electronics, Proceedings, 2004, : 189 - 192
- [9] ELECTRICAL DEGRADATION OF AL/TIW/COSI2 SHALLOW JUNCTIONS [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1991, 9 (01): : 69 - 73