Live Demonstration: High level Software and Hardware synthesis of dataflow programs

被引：0

作者：

Bezati, Endri ^{[1
]}

Roquier, Ghislain ^{[1
]}

Mattavelli, Marco ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

来源：

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes and demonstrates a toolchain which enables HW-SW co-synthesis from a single high-level dataflow program. This toolchain does not only enable rapid-prototyping of complex designs, but also provides a complete system integration framework including synthesis of SW-HW interconnect. This framework minimizes the designer efforts for a low level implementation. A co-design example of a JPEG codec is demonstrated using a high-level dataflow language, named CAL.

引用

页码：660 / 660

页数：1

共 50 条

[1] Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs
Roquier, Ghislain
Bezati, Endri
Mattavelli, Marco
[J]. JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, 2012, 2012
[2] Rapid prototyping of dataflow programs on hardware/software architectures
Eisenring, M
Teich, J
Thiele, L
[J]. PROCEEDINGS OF THE THIRTY-FIRST HAWAII INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES, VOL VII: SOFTWARE TECHNOLOGY TRACK, 1998, : 187 - 196
[3] METHODOLOGY FOR THE HARDWARE/SOFTWARE CO-DESIGN OF DATAFLOW PROGRAMS
Roquier, Ghislain
Thavot, Richard
Mattavelli, Marco
[J]. 2011 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2011, : 174 - 179
[4] EFFICIENT SOFTWARE SYNTHESIS OF DYNAMIC DATAFLOW PROGRAMS
Yviquel, H.
Sanchez, A.
Jaaskelainen, P.
Takala, J.
Raulet, M.
Casseau, E.
[J]. 2014 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2014,
[5] High-Level Synthesis of Dataflow Programs for Signal Processing Systems
Bezati, Endri
Mattavelli, Marco
Janneck, Jorn W.
[J]. 2013 8TH INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS (ISPA), 2013, : 750 - +
[6] High-level system synthesis and optimization of dataflow programs for MPSoCs
Bezati, E.
Brunet, S. Casale
Mattavelli, M.
Janneck, J. W.
[J]. 2016 50TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, 2016, : 417 - 421
[7] Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs
Jerbi, Khaled
Raulet, Mickael
Deforges, Olivier
Abid, Mohamed
[J]. VLSI DESIGN, 2012,
[8] High-Level Synthesis of Dynamic Dataflow Programs on heterogeneous MPSoC platforms
Bezati, Endri
Casale-Brunet, Simone
Mattavelli, Marco
Janneck, Jorn W.
[J]. PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (SAMOS), 2016, : 227 - 234
[9] Synthesizing Hardware from Dataflow Programs
Janneck, Joern W.
Miller, Ian D.
Parlour, David B.
Roquier, Ghislain
Wipliez, Matthieu
Raulet, Mickael
[J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2011, 63 (02): : 241 - 249
[10] System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures
Véstias, MP
Neto, HC
[J]. 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, 2002, : 130 - 137

← 1 2 3 4 5 →