Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control

This paper presents a technique, alternative to performance-driven synthesis, that allows to drastically increase the average throughput of combinational logic blocks by transforming fixed-latency units into variable-latency ones that run with a faster clock cycle. The transformation is fully automatic and can be used in conjunction with traditional design techniques, such as pipelining, to improve the overall performance of speed-critical systems. Results, obtained on a large set of benchmark circuits, are very promising.