Maximizing the Performance of 650 V p-GaN Gate HEMTs: Dynamic RON Characterization and Gate-Drive Design Considerations

This paper presents a systematic characterization of a 650 V/13 A enhancement-mode GaN power transistor with p-GaN gate. Static and dynamic device characteristics are measured by taking into account of trapping induced effects such as current collapse and threshold voltage instability. Switching performance is evaluated up to 400 V, 10 A using a custom designed double-pulse test circuit. Optimal gate drive conditions are proposed to minimize the influence of adverse trapping effects on circuit performance while preventing the device from excessive gate stress. Moreover, gate drive circuit design and board layout considerations addressing the fast switching characteristics of GaN devices are also discussed.