650 V p-GaN Gate Power HEMTs on 200 mm Engineered Substrates

被引:0
|
作者
Geens, Karen [1 ]
Li, Xiangdong [2 ]
Zhao, Ming [1 ]
Guo, Weiming [1 ]
Wellekens, Dirk [1 ]
Posthuma, Niels [1 ]
Fahle, Dirk [3 ]
Aktas, Ozgur [4 ]
Odnoblyudov, Vlad [4 ]
Decoutere, Stefaan [1 ]
机构
[1] IMEC, B-3001 Leuven, Belgium
[2] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium
[3] AIXTRON SE, D-52134 Herzogenrath, Germany
[4] Qromis Inc, Santa Clara, CA USA
关键词
p-GaN; HEMT; engineered substrates; 650; V;
D O I
10.1109/wipda46397.2019.8998922
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Engineered substrates with a poly-AlN core, thermally matched to the (Al)GaN buffer, are promising to reconcile the use of high-yield GaN wafers with the use of thick buffers (>= 650 V) on large scale substrates (>= 200 mm). We successfully managed to fabricate 650 V p-GaN gate power HEMTs on 200 mm engineered substrates with excellent performance and reliability. The 5.6 mu m (Al)GaN epitaxy stack shows low dispersion within +/- 10% after a -650 V/10 s back-gating stress. The fabricated power HEMTs with a gate-to-drain distance of 16 mu m show a threshold voltage of 3.6 V (at maximum transconductance), a low ON-resistance of 15 Omega.mm, and a low OFF-state drain leakage below 1 mu A/mm up to 650 V at 150 degrees C. The device reliability was finally validated by high temperature reverse bias (HTRB) and high temperature gate bias (HTGB) stress tests.
引用
收藏
页码:297 / 301
页数:5
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