Silicon resonant tunneling metal-oxide-semiconductor transistor for sub-0.1 μm era

被引：0

作者：

Matsuo, N ^{[1
]}

Takami, Y

Nozaki, T

Hamada, H

机构：

[1] Yamaguchi Univ, Dept Elect & Elect Engn, Ube, Yamaguchi 7558611, Japan

[2] Sanyo Elect Co Ltd, Microelect Res Ctr, Gifu 5030195, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2002年 / E85C卷 / 05期

关键词：

SRTMOST; sub-0.1 mu m; logic circuit;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel. is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 mum era, The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.

引用

页码：1086 / 1090

页数：5

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