A detailed analysis of CMOS SRAM's with gate oxide short defects

被引：14
|
作者：
Segura, J [1 ]
Rubio, A [1 ]
机构：
[1] UNIV POLITECN CATALUNYA,DEPT ELECT ENGN,ES-08034 BARCELONA,SPAIN
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 10期
关键词：
defect modeling; logic testing; parametric testing; RAM circuits;
D O I：
10.1109/4.634662
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Using a model of gate oxide short defects, previously developed and validated experimentally, we investigate the behavior of CMOS SRAM memories having this defect. Faulty behaviors caused by gate oxide shorts are characterized classifying those that may cause a logic malfunction and those that degrade the memory operation without causing a logic error. Merits of SRAM test algorithms to detect gate oxide shorts are analyzed, identifying which are effective in terms of coverage and test cost.
引用
收藏
页码：1543 / 1550
页数：8
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