共 50 条
- [32] Patterned Wafer Geometry(PWG) metrology for improving process-induced overlay and focus problems OPTICAL MICROLITHOGRAPHY XXIX, 2016, 9780
- [33] WAFER DESIGN AND CHARACTERIZATION FOR INTEGRATED-CIRCUIT PROCESSES ACS SYMPOSIUM SERIES, 1985, 290 : 310 - 333
- [35] Improved Device Overlay by Litho Aberration Tracking with Novel Target Design for DRAM METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXXIV, 2020, 11325
- [36] REALTIME WAFER CHARACTERIZATION FOR MAINTAINING MAXIMUM REGISTRATION ACCURACY AND MAXIMUM TOOL THROUGHPUT. IBM technical disclosure bulletin, 1984, 27 (06):
- [37] Matching between simulations and measurements as a key driver for reliable overlay target design METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXXII, 2018, 10585
- [38] The novel advanced process control to eliminate AlCu-PVD induced overlay shift METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXI, PTS 1-3, 2007, 6518
- [39] Monitoring Process-Induced Overlay Errors through High-Resolution Wafer Geometry Measurements METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXVIII, 2014, 9050