Improvement of Scheduling Efficiency Using Heuristic Methods and Simulation Technique in Electronic Assemblies Industry Production

The objective of this research is to reduce the makespan error in production planning by providing a proper sequencing process which will lead to the minimization of overall processing time, or makespan. The company selected as a case study is involved in flowshop manufacturing of flex cable circuit, with full plate production using a two-sided assembly line as part of roll-to-roll processing. The problem encountered was a 20% error in job completion between production planning and real production. Improper job sequencing caused a long wait for the machine in the manufacturing station, which resulted in a long makespan time. Developing a model by using Arena simulation can reduce the makespan error in production planning. The model is validated by using hypothesis testing (t-test), comparing makespan of real production and makespan of simulation at a 95% significance level. The production line is flows hop manufacturing, which presents a non-polynomial hard problem that is difficult to solve. Three heuristic scheduling methods are Palmer, Gupta, and CDS (Campbell, Dudek and Smith). They are used to compare with the preprocess scheduling for 13 weeks, in order to provide a proper scheduling method and a minimum makespan. The results showed that the simulation technique improved production planning by reducing the error rate from 12.80% to 5.04%. Moreover, the CDS heuristic sequencing method provided the maximum reduction in makespan (at a 95 % significance level).