Efficient path selection for delay testing based on path clustering

被引：6

作者：

Tani, S ^{[1
]}

Teramoto, M ^{[1
]}

Fukazawa, T ^{[1
]}

Matsuhiro, K ^{[1
]}

机构：

[1] Nippon Telegraph & Tel Corp, Network Innovat Labs, Yokosuka, Kanagawa 2390847, Japan

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1999年 / 15卷 / 1-2期

关键词：

delay testing; path delay; delay fault; clustering;

D O I：

10.1023/A:1008307516109

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we introduce a way of modeling the differences between the calculated delays and the real delays, and propose an efficient path selection method for path delay testing based on the model. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbances. In order to make precise judgment under this ambiguity, the delays of only the unshared segments of the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. The experiments used the delays of gates and interconnects, which were calculated from the layout data of ISCAS85 benchmark circuits using a real cell library. Experimental results show the method selects only about one percent of the paths selected by the most popular method.

引用

页码：75 / 85

页数：11

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