CMOS CIRCUIT DESIGN OF A TAKAGI-SUGENO FUZZY LOGIC CONTROLLER

被引:0
|
作者
Shan, Weiwei [1 ]
Liang, Yan [2 ]
Jin, Dongming [2 ]
机构
[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Peoples R China
[2] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
关键词
CMOS; analog circuit; fuzzy logic controller; membership function; CONTROL-SYSTEMS; CURRENT-MODE;
D O I
10.1142/S0218126609005009
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a low power CMOS analog integrated circuit of a Takagi-Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defuzzification is presented without using a division circuit. Based on these blocks, a two-input one-output singleton fuzzy controller with nine rules is designed under a CMOS 0.6 mu m standard technology provided by CSMC. HSPICE simulation results show that this controller reaches an accuracy of +/-3% with power consumption of only 3.5mW (at +/-2.5V). The speed of this controller goes up to 0.625M Fuzzy Logic Inference per Second (FLIPS), which is fast enough for real-time control.
引用
收藏
页码:841 / 856
页数:16
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