Fine pitch high pin count AlN LGA package

被引:0
|
作者
Asai, H
Kudo, J
Yano, K
Yasumoto, T
Kimura, K
Iyogi, K
Monma, J
Yamaguchi, H
Iwase, N
机构
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This work studied ways to reduce a flip chip assembling cost. It was hypothesized that low cost assembling would be achieved by lowering the bump height on a chip and by eliminating an underfilling work which is incorporated to assure solder joint reliability. Among several candidates for package materials such as plastic, metals, and ceramics, aluminum nitride (AlN) was examined to reduce a flip chip assembling cost. In this report, an AlN LGA (land grid array) package was manufactured and evaluated on its flatness of a chip attaching area and on electrical characteristics. Flatness was found to be low (5.5 mu m). The package showed possibility to use a chip with low bumps. AlN also showed high solder joint reliability with a low bump of 27 mu m m. This is because coefficient of thermal expansion (CTE) of AlN is close to that of silicon (Si). It was found that an AlN package was a possible candidate for establishing a lower bump flip chip assembly compared with a package made of plastic or alumina. The plating technology used in this AlN package was proved to be applicable for a fine pitch flip chip assembly.
引用
收藏
页码:299 / 302
页数:4
相关论文
共 50 条
  • [1] JUSTIFICATION OF TAB AS THE FINE PITCH PACKAGE FOR HIGH LEAD COUNT ICS
    VOSS, S
    PROCEEDING OF THE TECHNICAL PROGRAM OF NEPCON WEST 89, VOLS 1 AND 2, 1989, : 1202 - 1209
  • [2] Molded Chip Scale Package for high pin count
    Baba, S
    Tomita, Y
    Matsuo, M
    Matsushima, H
    Ueda, N
    Nakagawa, O
    46TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1996 PROCEEDINGS, 1996, : 1251 - 1257
  • [3] Molded chip scale package for high pin count
    Baba, S
    Tomita, Y
    Matsuo, M
    Matsushima, H
    Ueda, N
    Nakagawa, O
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1998, 21 (01): : 28 - 34
  • [4] Package-on-Package with Very Fine Pitch Interconnects for High Bandwidth
    Mohammed, Ilyas
    Co, Reynaldo
    Katkar, Rajesh
    2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 922 - 928
  • [5] Is TAB the right package for high-pin-count devices?
    Prasad, Ray P., 1600, IHS Publ Group, Libertyville, IL, United States (09):
  • [6] High performance ceramic QFP with fine pitch and high lead count
    Nakatsuka, Yasuo
    Morita, Yasuyuki
    Fujii, Masafumi
    Ohtani, Hiroshi
    Takahashi, Eiji
    Sumitomo Metals, 1993, 45 (02): : 165 - 172
  • [7] PIN COUNT HITS 40 IN SMALL PACKAGE
    LYMAN, J
    ELECTRONICS-US, 1981, 54 (23): : 46 - 47
  • [8] HIGH PIN-COUNT ASICS MAY GET NEW JEDEC PACKAGE
    NAEGELE, T
    ELECTRONICS, 1986, 59 (34): : 36 - 36
  • [9] Development and evaluation of a high performance fine pitch SODIMM socket package
    Li, P
    Martinez, J
    Tang, J
    Priore, S
    Hubbard, K
    Xue, J
    54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1161 - 1166
  • [10] A High Performance Package with Fine-Pitch RDL Quality Management
    Fang, Jen-Kuang
    Fong, Cher-Min
    Chen, Jhao-Cheng
    Chang, Huang-Hsieh
    Lu, Wen-Long
    Yang, Peng
    Tu, Hung-Jung
    Huang, Min-Lung
    IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 78 - 83