Contention resolution using multi-stage fiber delay line buffer in a photonic packet switch

We focus on contention resolution using an optical fiber delay line (FDL) buffer in a photonic packet switch. A scheduler for contention resolution may not have a high-speed electronic processor, which limits performance of a photonic packet switch. We thus propose a multi-stage buffer based on tree structure. The buffer has multiple schedulers to compensate for the slow processing speed of each scheduler. We show the performance of the multistage buffer with respect to packet loss probability through simulation experiments. As a result, we find that performance of a multistage buffer is strongly affected by the small number of FDLs in the first stage. We also show the number of FDLs in a multi-stage buffer needed to get the same performance as a high-speed one-stage buffer.