An IA-32 Processor with a Wide Voltage Operating Range in 32nm CMOS

被引：0

作者：

Ruhl, Gregory ^{[1
]}

Dighe, Saurabh ^{[1
]}

Jain, Shailendra ^{[1
]}

Khare, Surhud ^{[1
]}

Yada, Satish ^{[1
]}

Ambili, V ^{[1
]}

Salihundam, Praveen ^{[1
]}

Ramani, Shiva ^{[1
]}

Muthukumar, Sriram ^{[1
]}

Srinivasan, M. ^{[1
]}

Kumar, Arun ^{[1
]}

Kumar, Shasi ^{[1
]}

Ramanarayanan, Rajaraman ^{[1
]}

Erraguntla, Vasantha ^{[1
]}

Howard, Jason ^{[1
]}

Vangal, Sriram ^{[1
]}

Aseron, Paolo ^{[1
]}

Wilson, Howard ^{[1
]}

Borkar, Nitin ^{[1
]}

机构：

[1] Intel Labs, Microprocessor & Programming Res, Berkeley, CA USA

来源：

2012 IEEE HOT CHIPS 24 SYMPOSIUM (HCS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页数：37

共 50 条

[21] High Frequency Low Voltage 32nm node CMOS Rectifier for Energy Harvesting in Implantable Devices
Khan, Mohd Tauheed
Khan, Munna
Hasan, Mohd
[J]. 2015 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2015,
[22] Prefetching Strategy for Address Translation in IA-32 Emulation
Jiang, Liehui
Chen, Haifeng
Lu, Jianping
Zhao, Yuchun
[J]. PRACTICAL APPLICATIONS OF INTELLIGENT SYSTEMS, 2011, 124 : 703 - 708
[23] 40V MESFETs Fabricated on 32nm SOI CMOS
Lepkowski, William
Wilk, Seth J.
Kam, J.
Thornton, Trevor J.
[J]. 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
[24] Material Loss Impact on Device Performance for 32nm CMOS And Beyond
Kirkpatrick, Brian K.
Chambers, James J.
Prins, Steven L.
Riley, Deborah J.
Wade Xiong, Weize
Wang, Xin
[J]. ULTRA CLEAN PROCESSING OF SEMICONDUCTOR SURFACES IX, 2009, 145-146 : 245 - 248
[25] A Nanogap Transducer Array on 32nm CMOS for Electrochemical DNA Sequencing
Hall, Drew A.
Daniels, Jonathan S.
Geuskens, Bibiche
Tayebi, Noureddine
Credo, Grace M.
Liu, David J.
Li, Handong
Wu, Kai
Su, Xing
Varma, Madoo
Elibol, Oguz H.
[J]. 2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 288 - U400
[26] Revolutionary Nanoelectronic Devices and Processes for Post 32nm CMOS Era
Nishi, Yoshio
[J]. ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 3 - 14
[27] IA-32 execution layer:: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems
Baraz, L
Devor, T
Etzion, O
Goldenberg, S
Skaletsky, A
Wang, Y
Zemach, Y
[J]. 36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 2003, : 191 - 201
[28] 32nm overlay improvement capabilities
Eichelberger, Brad
Huang, Kevin
O'Brien, Kelly
Tien, David
Tsai, Frank
Minvielle, Anna
Singh, Lovejeet
Schefske, Jeffrey
[J]. OPTICAL MICROLITHOGRAPHY XXI, PTS 1-3, 2008, 6924
[29] Technology options for lithography at 32nm
Harned, Noreen
Van De Mast, Frank
[J]. EuroAsia Semiconductor, 2007, 29 (10): : 23 - 27
[30] Optical lithography for the 32nm node
Sewell, H
McCafferty, D
Wagner, C
Markoya, L
[J]. JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 2005, 18 (05) : 579 - 586

← 1 2 3 4 5 →