COTS-Based High-Performance Computing for Space Applications

被引：16

作者：

Esposito, S. ^{[1
]}

Albanese, C. ^{[2
]}

Alderighi, M. ^{[3
]}

Casini, F. ^{[2
]}

Giganti, L. ^{[4
]}

Esposti, M. L. ^{[4
]}

Monteleone, C. ^{[5
]}

Violante, M. ^{[1
]}

机构：

[1] Politecn Torino, I-10129 Turin, Italy

[2] Sanitas EG Srl, I-20133 Milan, Italy

[3] Ist Nazl Astrofis INAF, I-20133 Milan, Italy

[4] Thales Alenia Space Italia, I-20064 Milan, Italy

[5] ESA ESTEC, NL-2201 Noordwijk, Netherlands

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2015年 / 62卷 / 06期

关键词：

Central processing unit (CPU); commercial off the shelf (COTS); fault injection; memory encoding; memory protection; single-event upset (SEU); software-implemented fault tolerance (SIFT); space applications; watchdog processor; watchdog timer; ERROR-DETECTION; DHRYSTONE; SOFTWARE;

D O I：

10.1109/TNS.2015.2492824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Commercial-off-the-shelf devices are often advocated as the only solution to the increasing performance requirements in space applications. This paper presents the solutions developed in the frame of the European Space Agency's HiRel program, concluded in December 2014, where a number of techniques proposed in the past 10 years have been used to design a highly reliable system, which has been selected for forthcoming space missions. This paper presents the system architecture, describes performed evaluations, and discusses the results.

引用

页码：2687 / 2694

页数：8

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