Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

被引：18
|
作者：
Sharaf, KM
Elmasry, MI
机构：
[1] VLSI Research Group, Dept. of Elec. and Comp. Engineering, University of Waterloo
[2] AinShams University, Cairo
[3] Cairo University, Cairo
[4] University of Ottawa, Ottawa, Ont.
[5] Bell-Northern Research, Ottawa, Ont.
[6] Dept. of Elec. and Comp. Engineering, University of Waterloo, Waterloo, Ont.
[7] AT and T Bell Labs., GE
[8] Micro Components Organization, Burroughs Corporation (Unisys), San Diego, CA
[9] Kuwait University, Kuwait, Swiss Fed. Institute of Technology, Lausanne
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 02期
基金：
加拿大自然科学与工程研究理事会;
关键词：
D O I：
10.1109/4.487997
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented, The analytical delay model accounts for all the device parasitics and the device sizes of the two levels, Moreover, high-current effects are also considered in the developed model, Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay), A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.
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页码：202 / 211
页数：10
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