Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

被引：0

作者：

Hemmat, Maedeh ^{[1
]}

Kamal, Mehdi ^{[1
]}

Afzali-Kusha, Ali ^{[1
]}

Pedram, Massoud ^{[2
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran, Iran

[2] Univ Southern Calif, Dept Elect Engn, Los Angeles, CA 90089 USA

来源：

VLSI-SOC: SYSTEM-ON-CHIP IN THE NANOSCALE ERA - DESIGN, VERIFICATION AND RELIABILITY | 2017年 / 508卷

关键词：

Tunnel FET; Reliability issues; Process variation; Low power design; Hybrid TFET-MOSFET designs; Soft error; LOW-POWER; PERFORMANCE; RELIABILITY; DESIGNS;

D O I：

10.1007/978-3-319-67104-8_3

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work, to improve the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of process variations as well as their soft-error resiliency, we propose replacing some of TFET-based gates by MOSFET-based ones. The effectiveness of the proposed TFET-MOSFET hybrid implementation of the circuits are investigated by first studying the impacts of the process variation on the performances (I-V characteristics) of both homojunction InAs TFETs and MOSFETs. Next, to analyze the soft error rate of the circuits, the particle hit-induced transient current profiles of these devices are extracted. Based on these studies, a hybrid TFET-MOSFET circuit design approach which improves the reliability and soft-error resiliency compared to those of pure TFET-based circuits is suggested. Finally, the efficacy of the design approach is investigated by applying it to some circuits of ISCAS' 89 benchmark package.

引用

页码：41 / 59

页数：19