Hierarchical cache coherency protocol in a multi-level multiprocessors system

Shared memory multiprocessors have recently become popular due to their cost effectiveness and simplicity in implementation. Building multiprocessor system with cheap commercially available chips and high speed cache memory is a viable alternative to attaining higher performance. Moreover, multiprocessor systems have a much better price/performance ratio than a single large centralized system. However, multiprocessor system's performance is directly related to cache performance. One of the key performance issues of such system is the solution to the cache coherence problem. The choice of the coherence mechanism is dependent on the design architecture of the intended multiprocessor system. This paper presents a new scalable multiprocessor architecture that implement hierarchy of caches on multi-level bus. A new hardware based cache coherency protocol to maintain coherency of data in the system is presented. The architecture defines private common bus in each cluster of processors where as communication between the clusters takes place through the shared cache and main bus. Types of necessary bus transactions are also presented.