Maximum power-up current estimation in combinational CMOS circuits

The continuing decrease in feature size and increase in chip density is causing leakage current to be a major contributor to power dissipation in integrated circuits. A viable approach to the reduction of leakage current is to use power cut-off or gating techniques. In power gating, a PMOS sleep transistor is used to turn-on or turn-off the V-dd source to the circuit block. In combinational circuits, the maximum power up current depends only on the input vector that wakes up the circuit from its sleep mode. In this work, we formulate the problem of estimating the maximum power-up current as an integer linear programming (ILP) problem and use advanced Boolean satisfiability (SAT) and generic ILP solvers. Results indicate that generic ILP solvers are very useful in estimating the maximum power-up current.