Development methodology of ASIP based on Java']Java byte code using HW/SW co-design system for processor design

被引：1

作者：

Yanagisawa, H ^{[1
]}

Uehara, M ^{[1
]}

Mori, R ^{[1
]}

机构：

[1] Toyo Univ, Dept Informat & Comp Sci, Kawagoe, Saitama, Japan

来源：

24TH INTERNATIONAL CONFERENCE ON DISTRIBUTED COMPUTING SYSTEMS WORKSHOPS, PROCEEDINGS | 2004年

关键词：

H-W/SW codesign system; ISA; ASIP; !text type='Java']Java[!/text] processor; C-DASH;

D O I：

10.1109/ICDCSW.2004.1284129

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To develop an ASIP (Application Specific Instruction set Processor), development of HW (hardware) and development of SWDE (software development environments) are required. Separate develops of HW and SWDE in a short time are difficult. So HW/SW co-design system is necessary rapid develop of ASIPs. We have developed C-DASH(C-like Design Automation Shell), which is a HW/SW co-design system for designing processors based on ISA (Instruction Set Architecture). This paper describes the HW/SW co-design system C-DASH, along with a description of a java processor that directly executes Java byte code is given as an example.

引用

下载

页码：831 / 837

页数：7

共 50 条

[41] Remote Embedded Simulation System for SW/HW Co-design Based On Dynamic Partial Reconfiguration
Gu, Jiaqi
Wang, Ruoyao
Wang, Jian
Lai, Jinmei
Duan, Qinghua
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 402 - 405
[42] Co-design group looks to close gap between system, HW/SW
不详
ELECTRONIC DESIGN, 1998, 46 (01) : 30 - 30
[43] A New Hw/Sw Co-Design Method For Multiprocessor System On Chip Applications
Nita, Iulian
Lazarescu, Vasile
Constantinescu, Rodica
ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, 2009, : 253 - 256
[44] Hw-sw co-design of mpsoc using fgpa ip cores
Nita, Iulian
Zdru, Gabriel
1600, (75): : 135 - 150
[45] HW-SW CO-DESIGN OF MPSOC USING FGPA IP CORES
Nita, Iulian
Zdru, Gabriel
UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, 2013, 75 (01): : 135 - 150
[46] Hardware architecture for Java']Java in a hardware/software co-design of the virtual machine
Kent, KB
Serra, M
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS: ARCHITECTURES, METHODS AND TOOLS, 2002, : 20 - 27
[47] HW/SW Co-Design and Co-Optimizations for Deep Learning
Marchisio, Alberto
Putra, Rachmad Vidya Wicaksana
Hanif, Muhammad Abdullah
Shafique, Muhammad
WORKSHOP PROCEEDINGS 2018: INTELLIGENT EMBEDDED SYSTEMS ARCHITECTURES AND APPLICATIONS (INTESA), 2018, : 13 - 18
[48] Accelerating Accurate Fault Tree Analysis Using HW/SW Co-Design
Cheshmikhani, Elham
Zarandi, Hamid R.
Aliee, Hananeh
2014 60TH ANNUAL RELIABILITY AND MAINTAINABILITY SYMPOSIUM (RAMS), 2014,
[49] An HW/SW co-design approach for Neuro-Fuzzy hardware design
Chiaberge, M
Miranda, E
Reyneri, LM
PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, MICORNEURO'99, 1999, : 332 - 337
[50] Exploring processor design options for Java']Java-based middleware
Karlsson, M
Hagersten, E
Moore, KE
Wood, DA
2005 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSSING, PROCEEDINGS, 2005, : 59 - 68

← 1 2 3 4 5 →