Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits

Rapid Single Quantum Flux (RSFQ) logic, based on Josephson Junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of CMOS. Since it uses fabrication processes with large feature sizes, the defect density for RSFQ is dramatically lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific non-idealities become the major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly-distorted pulses are interpreted logically correctly by cells, but the timings is affected. Therefore, timing verification and delay testing increase in importance in RSFQ. In this paper, we address several radically new phenomena in RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by process variations. We then propose a completely new ATPG paradigm which utilizes these new phenomena to select target delay sub-paths and generate test patterns that are guaranteed to excite the worst-case delay along each target delay sub-path. Finally, we present Monte Carlo simulation results for benchmark circuits with process variations to demonstrate the effectiveness of the vectors generated by our new ATPG.