A cost effective interconnection network for reconfigurable computing processor in digital signal processing applications

被引：0
|
作者：
Lai, Yeong-Kang [1 ]
Chen, Lien-Fei [1 ]
Chen, Jian-Chou [1 ]
Chiu, Chun-Wei [1 ]
机构：
[1] Natl Chung Hsing Univ, Dept Elect Engn, Taichung 402, Taiwan
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2006年 / E89C卷 / 11期
关键词：
interconnection; digital signal processing; reconfigurable computing architecture;
D O I：
10.1093/ietele/e89-c.11.1674
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism, applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.
引用
收藏
页码：1674 / 1675
页数：2
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