Picosecond resolution programmable delay line

被引:8
|
作者
Suchenek, Mariusz [1 ]
机构
[1] Warsaw Univ Technol, Inst Elect Syst, PL-00660 Warsaw, Poland
关键词
programmable delay line; picosecond;
D O I
10.1088/0957-0233/20/11/117005
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.
引用
收藏
页数:5
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