Design of Dopingless GaN Nanowire FET with Low 'Q' for High Switching and RF Applications

被引:19
|
作者
Singh, Sarabdeep [1 ]
Raman, Ashish [1 ]
机构
[1] Dr BR Ambedkar Natl Inst Technol, Dept Elect & Commun, VLSI Design Lab, Jalandhar 144011, Punjab, India
关键词
Charge plasma; Gallium nitride (GaN); Short Channel effects; Nanowire; GATE-STACKED ARCHITECTURE; FIELD-EFFECT TRANSISTOR; DUAL-MATERIAL; JUNCTIONLESS TRANSISTOR; MOSFET; PERFORMANCE;
D O I
10.1007/s12633-020-00912-5
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
The unique properties like wide band gap and high electron mobility makes GaN an interesting material to be used in building devices at the nanoscale in recent times. This paper first time proposed a charge plasma (CP) based dopingless gate all around (GAA) GaN Nanowire FET (NWFET) (CP-GaN). The advantages of CP device over junctionless (JL) in NWFET structure along with properties of GaN material, results in a highly efficient structure of CP-GaN. The CP-GaN is compared with JL-GaN and silicon counterparts of CP & JL. Results reveal that CP-GaN is showing outstanding performance as I-on of 3.95 x 10(-5) A, I-off of 5.36 x 10(-13) A and I-on/I-off of 7.37 x 10(7). The proposed device CP-GaN shows better performance than CP-Si based device. When compared with JL-GaN, CP-GaN shows 55% less DIBL. The figure of merit Q = g(m)/SS of 0.85 mu S/mu m-dec/mV, is highest for our proposed CP-GaN. This makes CP-GaN an attractive design to be explored for high switching & low voltage applications with reduced SCEs and lower thermal budget. The other design parameters viz. gate length, gate dielectric, gate and source/drain work functions, nanowire radius and interface trap charges effect are also investigated for further optimization of the proposed design.
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页码:1297 / 1307
页数:11
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