Auto-tuned counter synchronisation in FPGA-based interpolation time digitisers

被引：1
|
作者：
Szplet, R. [1 ]
机构：
[1] Mil Univ Technol, Fac Elect, PL-00908 Warsaw 49, Poland
来源：
ELECTRONICS LETTERS | 2009年 / 45卷 / 13期
关键词：
D O I：
10.1049/el.2009.3362
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel method for auto-tuned synchronisation of the counter in interpolation time digitisers is described. A clock phase adjustment is utilised to avoid the metastability effect in the counter and to achieve the highest possible operating frequency in a given technology.
引用
收藏
页码：671 / 672
页数：2
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