Optimal Design of Full Subtractor using Particle Swarm Optimization with Aging Leader and Challenger Algorithm

被引:0
|
作者
Kumar, S. [1 ]
Prasad, P. K. [1 ]
Das, R. [1 ]
Kumar, A. [1 ]
Kar, R. [1 ]
Mandal, D. [1 ]
Ghoshal, S. P. [2 ]
机构
[1] NIT Durgapur, Dept Elect & Commun Engn, Durgapur 713209, W Bengal, India
[2] NIT Durgapur, Dept Elect Engn, Durgapur 713209, W Bengal, India
关键词
Combinational Circuit; Hunan Design Method; Matlab; DSCH3.5; Microwind3.1 Particle Swarm Optimization with Aging Leader and Challenger;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As the VLSI technology grows up, optimization is required to reduce the complexity, area and power of the digital circuits. In order to optimize the hardware requirement of digital combinational circuits, evolutionary techniques need to he enforced at various levels such as gate level and device level. This paper presents an efficient approach for the optimal design of a combinational logic circuit with a reduced gate count in MATLAB platform. The evolutionary optimization technique used is Particle Swarm Optimization with Aging Leader and Challenger (ALC-PSO). The results obtained after optimization of Full Subtractor circuit using ALC-PSO technique are shown to have a less number of gates compared to human design method. Later on that optimized circuit has been analysed by DSCH3.5 and Microwind3.1 VLSI CAD Tool. The results shown in this paper reflects that technology scaling decreases the area, delay and power consumption which are some of the major requirements of today's VLSI design.
引用
收藏
页码:1009 / 1012
页数:4
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