Hardware implementation of Variable Precision Multiplication on FPGA

A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size in to compute the multiplication of two numbers of n x m bits. These numbers are represented in the variable precision floating point format, but in this paper Only the mantissas are considered; the exponents are easily obtained by adding the exponents of the two operands to be multiplied. In this computing method of multiplication, the partial products are added as soon as they are computed, resulting in the use of the lowest memory for the storage of intermediate results, (i.e. the size of the result is of m x 2n bits). The Xilinx FPGA circuits, of Virtex-II families and greater, have interesting resources such as embedded Multipliers 18 x 18 bits, memory blocks (SelectRam) and early chain paths for the acceleration of the carry propagation and DCM blocks (Digital Clock Manager) to generate and control clocks. These resources have been advantageously used, in the implementation, to reduce the computation delay compared to the solution that uses only FPGA CLBs (Logic Blocks). Our architecture has been tailored to use these efficient resources and the resulting architecture is dedicated to compute the multiplication of operands of sizes ranging from 1 x 64 bits to 64 x 64 bits with a period of n(2) x 33 ns.