A power- and area-efficient SRAM core architecturt for super-parallel video processing

super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional muld-division SRAM can be eliminated. Consequently, the proposed SRAM reduces an area and power by 69% and 59%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (eight-division and 2-read port SRAM) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 mu W for QCIF 15-fps in a 130-nm technology.