A reconfigurable HW platform for high-speed digital test systems

In this work we present the study and the implementation of a Bit Error Rate Tester (BERT) for the performance analysis of digital communication systems with very high speed bit rate, up to 40 Gbit/s. A Bit Error Rate Tester is normally used to measure the most important performance parameter of a digital communication system that is the bit error probability. The approach to implement this system exploits some particular properties of the pseudo-random bit sequences: in fact the sequence generation and its reception will be implemented through algorithms with high parallelism. In this way we will have N parallel streams of data, each one with a bit rate of, for example, 40/N Gbit/s: with high parallelism we can avoid data processing architectures at high speed with remarkable lowest costs and much more easy implementation. The innovative aspect of this research is the development of a re-configurable platform with a flexible architecture for digital signal conditioning using state of the art programmable devices for very high-speed bit rate (from 1.25 Gbit/s to 40 Gbit/s). This platform is based on programmable devices such as DSP (Digital Signal Processor) and PLD (Programmable Logic Devices).