FPGA-based low-complexity high-throughput real-time hardware accelerator for robust watermarking

被引：5

作者：

Ge, Hangqi ^{[1
]}

Sha, Jin ^{[1
]}

机构：

[1] Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China

来源：

JOURNAL OF REAL-TIME IMAGE PROCESSING | 2019年 / 16卷 / 04期

关键词：

Real time; High throughput; Simplified DCT; IDCT; Robust watermarking;

D O I：

10.1007/s11554-019-00882-x

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents an FPGA-based hardware accelerator for robust watermarking. By applying some novel transformation techniques, the DCT/IDCT algorithm is simplified in a hardware-friendly way by replacing the original complex multiplication/division and nonlinear function (cosine function) with addition and shift operations. Moreover, the architecture of this real-time accelerator is proposed with pipeline technique to improve throughput and hardware efficiency. The entire design is implemented on FPGA, which achieves up to 3.2 GBps (Giga Bytes per second) throughput. Finally, the experimental results show that the proposed accelerator has good performance.

引用

页码：813 / 820

页数：8

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