IP Protection Platform Based on Watermarking Technique

被引：0
|
作者：
Du, Yun [1 ]
Ding, Yangshuo [1 ]
Chen, Yujie [1 ]
Gao, Zhiqiang [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 | 2009年
关键词：
Watermarking; IP; protection; netlist; layout;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Intellectual property (IP) block reuse is becoming the mainstream of System-on-Chip (SOC) design. However, the trade of IP blocks poses significant high security risks. Consequently IP protection becomes sensitive and urgent. In this paper, DesignMarker platform used for IP protection is proposed, which is based on watermarking technique. Both netlist-level watermarking module and layout-level watermarking module are integrated with this platform. Through this platform, watermarking message can be embedded into IP at netlist-level or layout-level with few overhead costs. What's more, the platform can be extended and improved with new watermarking modules.
引用
收藏
页码：287 / 290
页数：4
相关论文
共 50 条
  • [1] Watermarking technique for HDL-based IP module protection
    Lin, Min-Chuan
    Tsai, Guo-Ruey
    Wu, Chun-Rong
    Lin, Ching-Hui
    2007 THIRD INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING, VOL II, PROCEEDINGS, 2007, : 393 - 396
  • [2] A hierarchy watermarking technique for IP core protection
    Sun, GY
    Gao, ZQ
    Ni, M
    2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 1035 - 1038
  • [3] Watermarking based IP core protection
    Fan, YC
    Tsao, HW
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 181 - 184
  • [4] A watermarking system for IP protection by buffer insertion technique
    Sun, Guangyu
    Gao, Zhiqiang
    Xu, Yi
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 671 - +
  • [5] A detection-driven watermarking technique for VLSI IP protection
    Kwak, S.
    Lee, J.
    Har, D.
    IMECS 2006: INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS, 2006, : 249 - +
  • [6] IPP watermarking technique for IP core protection on FPL devices
    Castillo, Encarnacion
    Parrilla, Luis
    Garcia, Antonio
    Loris, Antonio
    Meyer-Baese, Uwe
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 487 - 492
  • [7] Watermarking ICs for IP protection
    Newbould, RD
    Irby, DL
    Carothers, JD
    Rodriguez, JJ
    Holman, WT
    ELECTRONICS LETTERS, 2002, 38 (06) : 272 - 274
  • [8] Detector-based watermarking technique for soft IP core protection in high synthesis design level
    Ni, M
    Gao, ZQ
    2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS: VOL 1: COMMUNICATION THEORY AND SYSTEMS, 2005, : 1348 - 1352
  • [9] Constraint-based watermarking technique for hard IP core protection in physical layout design level
    Ni, M
    Gao, ZQ
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1360 - 1363
  • [10] Constraint-based watermarking techniques for design IP protection
    Kahng, AB
    Lach, J
    Mangione-Smith, WH
    Mantik, S
    Markov, IL
    Potkonjak, M
    Tucker, P
    Wang, HJ
    Wolfe, G
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (10) : 1236 - 1252
12345