Fast bit parallel-shifted polynomial basis multipliers in GF(2n)

被引:44
|
作者
Fan, Haining [1 ]
Hasan, M. Anwar [1 ]
机构
[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada
关键词
finite field; irreducible polynomial; multiplication; polynomial basis; shifted polynomial basis;
D O I
10.1109/TCSI.2006.883855
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new nonpipelined bit-parallel-shifted polynomial basis multiplier for GF(2(n)) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results avaliable in the literature, and its gate delay is equal to T-A + [log(2) n]T-X, where T-A and T-X are the delay of one two-input AND and XOR gates, respectively. To the best of our knowledge, this is the first time that the gate delay bound T-A + [log(2) n] T-X is reached. For some irreducible pentanomials, its gate delay is equal to T-A + (1 + [log(2) n])T-X. NIST has recommended five binary fields for the elliptic curve digital signature algorithm applications: GF(2(163)), GF((233)), GF((283)), GF(2(409)), and GF(2(571)), but no irreducible trinomials exist for three degrees, viz., 163, 283 and 571. For the three corresponding binary fields, we show that the gate delay of the proposed multiplier is T-A + (1 + [log(2) n])T-X. This result outperforms the previously known results.
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页码:2606 / 2615
页数:10
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