Fast bit-parallel GF(2n) multiplier for all trinomials

被引：64

作者：

Fan, HN ^{[1
]}

Dai, YQ ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Comp Sci, Beijing 100084, Peoples R China

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2005年 / 54卷 / 04期

关键词：

finite field; multiplication; polynomial basis; irreducible trinomial;

D O I：

10.1109/TC.2005.64

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Based on a new representation of GF(2(n)), we present two multipliers for all irreducible trinomials. Space complexities of the multipliers match the best results. The time complexity of one multiplier is T-A - (1 + [log(2)n])T-X for all irreducible trinomials, where TA and TX are the delay of one 2-input AND and XOR gates, respectively.

引用

页码：485 / 490

页数：6

共 50 条

[1] Low complexity bit-parallel squarer for GF(2n) defined by irreducible trinomials
Park, Sun-Mi
Chang, Ku-Young
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (09) : 2451 - 2452
[2] New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2n)
Cho, Young In
Chang, Nam Su
Kim, Chang Han
Park, Young-Ho
Hong, Seokhie
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (10) : 1903 - 1908
[3] Speedup of bit-parallel Karatsuba multiplier in GF(2m) generated by trinomials
Li, Yin
Chen, Gong-liang
Li, Jian-hua
[J]. INFORMATION PROCESSING LETTERS, 2011, 111 (08) : 390 - 394
[4] A Chinese Remainder Theorem Approach to Bit-Parallel GF(2n) Polynomial Basis Multipliers for Irreducible Trinomials
Fan, Haining
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2016, 65 (02) : 343 - 352
[5] Efficient Bit-Parallel Multiplier for All Trinomials Based on n-Term Karatsuba Algorithm
Park, Sun-Mi
Chang, Ku-Young
Hong, Dowon
Seo, Changho
[J]. IEEE ACCESS, 2020, 8 : 173491 - 173507
[6] A survey of some recent bit-parallel GF(2n) multipliers
Fan, Haining
Hasan, M. Anwar
[J]. FINITE FIELDS AND THEIR APPLICATIONS, 2015, 32 : 5 - 43
[7] Bit-parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations
Mathe, Sudha Ellison
Boppanal, Lakshmi
[J]. IET CIRCUITS DEVICES & SYSTEMS, 2018, 12 (04) : 315 - 325
[8] Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials
Lee, CY
[J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (01): : 39 - 42
[9] Low space complexity CRT-based bit-parallel GF (2n) polynomial basis multipliers for irreducible trinomials
Zhang, Jiajun
Fan, Haining
[J]. INTEGRATION-THE VLSI JOURNAL, 2017, 58 : 55 - 63
[10] Low complexity bit-parallel normal bases multipliers for GF(2n)
Fan, H
Dai, Y
[J]. ELECTRONICS LETTERS, 2004, 40 (01) : 24 - 26

← 1 2 3 4 5 →